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...the world's most energy friendly microcontrollers
Bit
Name
Reset
Access
Description
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6
SWOSCBLOCK
0
RW
Software Oscillator Disable Block
Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it is not
already running.
Value
0
1
Description
Software is allowed to disable the selected WDOG oscillator. See CMU for detailed description. Note that also CMU
registers are lockable.
Software is not allowed to disable the selected WDOG oscillator.
5
EM4BLOCK
0
RW
Energy Mode 4 Block
Set to prevent the EMU from entering EM4
Value
0
1
Description
EM4 can be entered. See EMU for detailed description.
EM4 cannot be entered.
4
LOCK
0
RW
Configuration lock
Set to lock the watchdog configuration. This bit can only be cleared by reset.
Value
0
1
Description
Watchdog configuration can be changed.
Watchdog configuration cannot be changed.
3
EM3RUN
0
RW
Energy Mode 3 Run Enable
Set to keep watchdog running in EM3.
Value
0
1
Description
Watchdog timer is frozen in EM3.
Watchdog timer is running in EM3.
2
EM2RUN
0
RW
Energy Mode 2 Run Enable
Set to keep watchdog running in EM2
Value
0
1
Description
Watchdog timer is frozen in EM2.
Watchdog timer is running in EM2.
1
DEBUGRUN
0
RW
Debug Mode Run Enable
Set to keep watchdog running in debug mode.
Value
0
1
Description
Watchdog timer is frozen in debug mode.
Watchdog timer is running in debug mode.
0
EN
0
RW
Watchdog Timer Enable
Set to enabled watchdog timer.
12.5.2 WDOG_CMD - Command Register (Async Reg)
Offset
0x004
Reset
Access
Name
Bit Position
2011-04-12 - d0001_Rev1.10
124
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